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Was going through the Risc-V Vector ISA spec (as you do) and noticed this little gem:

Specifically the line "When 16-bit and 128-bit element widths are added, they will be also be treated as IEEE-754/2008-compatible values. "

Unless I'm miss interpreting this, is Risc-V indicating future *native* support for 128 bit integer and floating point?

On the other hand, because I'm that guy: GOSH DARN IT, WHY NOT SHIP FP16 AS PART OF V.1 😭
https://github.com/riscv/riscv-v-spec/releases/download/v1.0/riscv-v-spec-1.0.pdf

#HPC #BLAS #RiscV #FP16 #ASM
whether floating-point is supported, and for which element widths, is determined by the specific vector extension. The current set of
extensions include support for 32-bit and 64-bit floating-point values. When 16-bit and 128-bit element widths are added, they will be also be treated as IEEE-754/2008-compatible values. Other floating-point formats may be supported in future extension.


Hi!

To #introduce myself, I'm software for productive parallel programming in Python.

Use me to create parallel programs composed of Python functions and external components. Execute Parsl programs on any compute resource from laptops to #HPC supercomputers & #Cloud.

I'm open source (Apache-2.0), and currently funded by NSF & CZI.

Read more on https://parsl-project.org, try me via binder at https://mybinder.org/v2/gh/Parsl/parsl-tutorial/master, and find my source code at https://github.com/Parsl


No quote retoots/reblogs on Mastodon (see https://mastodon.social/@Gargron/99662106175542726) is a problem since I always add commentary/context/opinion while rebroadcasting #HPC news. Otherwise, what value am I adding before passing information along?
#hpc


Ah sí, para #Linus #Torvalds el #HPC es «pointless».
https://www.realworldtech.com/forum/?threadid=193189&curpostid=193190

Que la implementación de #Intel ha sido una absoluta cagada es cierto como una catedral de grande. Pero que tener buenas unidades de coma flotante es irrelevante ofende a cualquiera. Ya es una ganancia poder dejar para el final del desarrollo de kernels de aprendizaje automático la adición de toda la morralla del acelerador o biblioteca de paralelismo de turno.

#AMD ha implementado #AVX512 de forma usable.


Como diría M. Rajoy, los científicos hacen cosas. Desde luego no gracias a él, su equipo o sucesores. Si cumplieran con su deber para con el interés general aumentarían el presupuesto en ciencia en vez de en armas.

https://www.hpcwire.com/2022/09/02/using-exascale-supercomputers-to-make-clean-fusion-energy-possible/

#exascale #fusion #hpc
Blobby edge turbulence in a DIII-D tokamak plasma, causing a degradation in the plasma confinement at edge.

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